Materials with a high dielectric constant, referred to herein as high-k materials or as high-k gate materials, are utilized in high-k gate complementary metal oxide semiconductor (CMOS) technology. In CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs). In conventional high-k gate CMOS fabrication, the high-k material of the gate stack, specifically hafnium oxide dielectrics, are prone to re-growth. Further, the workfunction of the high-k gate material may shift if the high-k material is exposed to oxygen during processing or comes into contact with oxygen-containing materials, such as silicon dioxide, SiO2. Additionally, the gate stack can grow thicker as a result of the thermal budget and presence or contact of the hafnium with the SiO2.
In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address the needs. In CMOS devices employing high-k gate dielectric materials, suitable materials satisfying the work function requirements are needed. So far, identification of materials for a dual work function metal gate electrode system has presented some challenges. Moreover, finding high k gate stack materials suitable for gate first applications where the dielectric materials are subjected to high thermal budgets is a challenge.
The current state of the art in fabrication of high k gate stack transistors involves forming shallow trench isolation to separate nFET regions from pFET regions, depositing high k, metals, and poly silicon. The gate stack materials are then patterned using photolithographic techniques and reactive ion etching to form the gate electrode. Thus, in instances where the gate electrode is shared between nFET regions and pFET regions, the gate electrode will also be in contact with the SiO2 material from the shallow trench isolation. It may be possible to remove the high k materials from being in contact with the shallow trench isolation regions by a costly photo lithographic and etching technique. However, this technique would suffer the overlay and critical dimension variations inherent in photolithographic techniques.
In view of the above, there exists a need for reliable forming a semiconductor structure wherein the high-k material layer is precisely aligned to the active region in the silicon substrate and wherein the exposure of the high-k material to oxygen is minimized.